Method and apparatus for generating self contrasting character images

ABSTRACT

A subsystem of an apparatus that receives characterrepresentative signals and generates video control signals and keying control signals that are suitable for controlling a scanned display to present contrasting character images. A stroke generator means, responsive to the character-representative signals, generates a stroke of a character to be displayed. The stroke consists of a plurality of time sequential bits corresponding to a sequence of display events and a plurality of code bits that distinguish between contrasting portions of the sequence of display events. A decoding means is responsive to the time sequential bits and the code bits and generates keying control signals and video control signals that are suitable for controlling a scanned display to present contrasted images of characters to be displayed. In a preferred embodiment of the invention, the code bits are representative of the keying and video portions of the sequence of display events. The coding means produces signals that disable the generation of video signal during selected stroke portions, the code bits being determinative of which portions of the display event are to be disabled.

United States Eatent [1 1 Baron et al.

' Dec. 25, 1973 METHOD AND APPARATUS FOR GENERATING SELF CONTRASTINGCHARACTER IMAGES [75] Inventors: Stanley N. Baron, Stamford, Conn.;

I Stephen Kreinik, Monsey, NY.

[73] Assignee: Columbia Broadcasting System, Inc.,

New York, NY.

[22] Filed: Mar. 20, 1972 [21] Appl. No.: 236,428

[52] US. Cl 340/324 AD, 178/DIG. 34

[51] Int. Cl. G06t 3/14 [58] Field of Search 340/324 AD, 324 A;

178/5.8 R, DIG. 34

[56] References Cited UNITED STATES PATENTS 3,471,848 10/1969 Manber340/324 AD 3,109,166 10/1963 Kronenberg et al. 340/324 AD 3,573,7894/1971 Sharp et al 340/324 AD 2,138,577 11/1938 Gray l78/DlG. 34

2,990,450 6/1961 Treuhart 178/D1G. 34

Primary Examiner-John W. Caldwell Assistant ExaminerMarshall M. CurtisAttorney-Spencer E. Olson et al.

[ ABSTRACT A subsystem of an apparatus that receivescharacterrepresentative signals and generates video control signals andkeying control signals that are suitable for controlling a scanneddisplay to present contrasting character images. A stroke generatormeans, responsive to the character-representative signals, generates astroke of a character to be displayed. The stroke consists of aplurality of time sequential bits corresponding to a sequence of displayevents and a plurality of code bits that distinguish between contrastingportions of the sequence of display events. A decoding means isresponsive to the time sequential bits and the code bits and generateskeying control signals and video control signals that are suitable forcontrolling a scanned display to present contrasted images of charactersto be displayed. In a preferred embodiment of the invention, the codebits are representative of the keying and video portions of the sequenceof display events. The coding means produces signals that disable thegeneration of video signal during selected stroke portions, the codebits being determinative of which portions of the display event are tobe disabled.

19 Claims, 11 Drawing Figures space/r ans/c T/Ml/VG TIMI/V6 To 30/\ I T60/ 6/03 SPEC/F/ED CHARACTER I LEVEL mm gga I GENERATOR CHM/Ir s lI/VFORMAT/O/V E STROKE 6 I PORT/0N 20 I S 5 SENSOR L i even I eve/7 I II I 650 l I I I I 660 670 I I I I I I I P nnmzs ms SHIET 5 BF 9 BASICCLOCK I l l I SPACER 7'/M//V6 PULSE PATENTEDmzs I973 SHEET 9 BF 9 B E mN m S SCA/VL/NE /3 METHOD AND APPARATUS FOR GENERATING SELF CONTRASTINGCHARACTER IMAGES BACKGROUND OF THE INVENTION This invention relates tovideo display apparatus and, more particularly, to an apparatus forgenerating signals that are suitable for controlling a scanned displayto present contrasted character images such as edged title information.

There have been previously described various systems which convertdigital title information into video signals that are suitable fordisplay in readable form. Systems of this type are employed, forexample, to provide title information along on a display screen, such asis typically done with financial data. Title information may also begenerated for display in conjunction with conventional televisionpicture information. This is generally accomplished by combining thevideo picture and the title signal using known keying techniques.

In the type of system where title information is generated for displayin conjunction with conventional television picture information, araster-compatible character generator is generally employed. Thecharacter generator receives digitally coded character signals from aninput source, typically a keyboard. A number of coded character signals,representative of a number of characters to be displayed at a particulartime, are stored in a recirculating shift register. The shift registeris recirculated at a rate that is synchronized with the line rate of thetelevision raster scanning pattern. Character signals read out of therecirculating shift register are fed to a stroke generator portion ofthe character generator which, under precise timing constraints,produces character stroke signals that ultimately control the blankingand unblanking of a scanning beam in a display device. After being readout, each character signal is restored in the recirculating register tobe recalled when the next strokes of each character in the display roware generated. Character traces are formed on the display device by theblanking and unblanking f the scanning beam as the beam traverses thedisplay device. Each character is formed on the display as a series ofslices or strokes during successive scanlines. The retentivityof visionof the eye is relied upon to build up the impression of completecharacters from the separate character strokes produced during eachscanline.

When title information is to be displayed in conjunction withconventional picture video, the title strokes are inserted" in thepicture signal using a keying circult that effectively opens slots" inthe picture video and inserts the title strokes at some predeterminedbrightness level, generally white level. Resultant white characters areusually of satisfactory visibility. When, however, the picturebackground happens to also be white or near-white, the characters becomedifficult to distinguish from the background Consequently, it has becomecommon practice to employ an edging circuit" that produces contrastingoutlines around the displayed characters, usually a black outline aroundwhite characters. The edging function is generally accomplished in thefollowing manner:

The character stroke signals are fed to two pairs of delay lines, onepair of which is used to generate the edges on the left and right of thecharacter outlines (i.e., "horizontal edging") and the other pair usedto generate the edges on the top and bottom of the character outlines(i.e., vertical edging"). The two delay lines used to accomplishhorizontal edging have short inherent delays, for example nanosecondseach, that are representative of a single display picture element. Thesedelay lines are coupled in series so that three versions of the inputstroke signal are available; viz, an undelayed signal (called a leftsignal), a once delayed signal (called a main signal) and a twicedelayed signal (called a right signal). The left, main, and rightsignals are combined in a particular manner that results in a processedstroke that starts one picture element (about 150 nanoseconds) beforethe main signal and ends one picture element after the main signal. Theprocessed stroke is utilized to open a keying slot that is wider thanthe main signal. Thus, by inserting white video in accordance with themain signal, a white stroke having black edges on each side is formed.

The vertical edging is achieved in analagous manner except that delaysof one and two scanlines (i.e., 64 and 128 microseconds) are employed.In this case, top," main," and bottom signals are formed and thencombined in appropriate manner to provide a black edge above and belowwhite video. While white and black have been chosen for illustration,any selection of colors or shades can be used in this manner to producecontrasting characters and edges.

The conventional edging scheme just described is satisfactory in mostapplications, but does suffer certain disadvantages and limitations. Onedisadvantage, which is largely aesthetic in nature, is illustrated inFIG. 1, wherein there is shown a face view of the character F" as mightbe displayed by a system utilizing conventional edging circuitry. Thebody 10 of the letter is typically displayed as white video havingsurrounding black edges. The right and left edging, designated byreference numeral 11, is generated by the horizontal edging circuitrywhile the top and bottom edging 12, is generated by the vertical edgingcircuitry. A close observation reveals that the edging appears cut outat the sharp letter corners; in other words, the corners designated 13have no edging.

The absence of edging around the corners of the character followsdirectly from the fact that the small unedged voids are neither directlyabove, below, or on the side of white video. Consequently, the edgingcircuitry does not generate edges in these areas. This phenomenon servesto illustrate the basic disadvantage of conventional edging schemes;i.e., that the placement of edges is completely determined by the shapeof the main video. Thus, situations where it is desirable to havespecial edging or shading effects cannot be handled by conventionaledging equipments.

Accordingly, it is an object of this invention to provide an edgingsystem that is capable of generating fully edged characters and, mostimportantly, capable of generating special edging effects to the desiresof a user.

SUMMARY OF THE INVENTION The present invention is directed to asubsystem of an apparatus that receives character-representative signalsand generates video control signals and keying control signals that aresuitable for controlling a scanned display to present contrastingcharacter images. In accordance with the invention. there is provided astroke generator means responsive to character-representative signalsfor generating a stroke of a character to be displayed, the strokecomprising a plurality of time sequential bits corresponding to asequence of display events and a plurality of code bits that distinguishbetween contrasting portions of the sequence of display events. Furtherprovided are decoding means responsive to the time sequential bits andcode bits for generating keying control signals and video controlsignals suitable for controlling a scanned display to present contrastedimages of the characters to be displayed.

In a preferred embodiment of the invention the code bits arerepresentative of the keying and video portions of the sequence ofdisplay events. In this embodiment, the decoding means produces signalsthat disable the generation of a video signal during selected strokeportions. The code bits are determinative of which portions of thedisplay events are to be disabled.

Further features and advantages of the invention will become morereadily apparent from the following detailed description when taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I, referred to as background forthe invention, is a face view of a displayed character formed by asystem utilizing conventional edging circuitry;

FIG. 2 is a simplified block diagram of a rastercompatible charactergenerator system;

FIG. 3 illustrates the type of character patterns which can be formedwith stroke signal generated by the apparatus of FIG. 2;

FIG. 4 illustrates in-further detail the functioning of the strokegenerator portion of FIG. 2;

FIG. 5 is a block diagram of circuitry in accordance with the presentinvention;

FIG. 6 is a block diagram of the horizontal edge generator circuit ofFIG. 5;.

FIG. 7, consisting of FIGS. 7a and 7b, illustrates the timing associatedwith the production of contrasted characters in accordance with thecircuitry of FIG. 5;

FIG. 8 is a block diagram of the stroke portion sensor circuit of FIG.5;

FIG. 9 is a block diagram of circuitry in accordance with anotherembodiment of the invention; and

FIG. 10 illustrates the timing associated with the production ofcontrasted characters in accordance with the circuitry of FIG. 9.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 2, there isshown a simplified block diagram of a raster-compatible charactergenerator system which, in conjunction with components of the presentinvention, will be suitable for controlling a scanned display to presentcontrasted character images such as edged title information. Thecharacter generation system of FIG. 2 is of a particular type thatgenerates proportionally spaced characters, and is described in detailin the copending U. S. patent application Ser. No. 128,727 of StanleyBaron entitled Proportional Character Generator filed Mar. 29, 1971 andassigned to same assignee as the present invention. That application isincorporated herein by reference, and only portions of the previousdisclosure needed for a proper understanding of the present inventionwill be described in detail herein.

The basic units of the system of FIG. 2 are a recirculating storagemeans 100, a timing generator 200, a stroke generator 300, and a spacerdetector 400. Character-representative digital signals are received bythe recirculating storage means 100. These signals are typically inbinary form with, for example, a given six bit coded input signalrepresenting one of 64 (2) letters, numbers and symbols. The inputcharacterrepresentative signals may be derived, for example, from acomputer or from an input keyboard. The stroke generator 300 receivescertain signals from the other units and generates stroke bits suitablefor controlling a display to produce appropriate strokes or slices of acharacter represented at a particular time.

Before proceeding with the description of the system of FIG. 2, it isinstructive to illustrate the type of character patterns which can beformed with the stroke signals generated by that apparatus, as is donewith the aid of FIG. 3. The characters are depicted as being displayedon a display device having a television rastertype scanning pattern.With such a device the characters are generally displayed at a white orlight level, but the characters are shown in FIG. 3 as black on a whitebackground for each of illustration. The characters of FIG. 3 aregenerated without the use of prior art edging systems or the charactercontrasting equipment of the present invention, and are shown for thepurpose of describing the manner in which character strokes are used toform the desired letters, numbers or symbols.

The scanning pattern of FIG. 3 may be a conventional interlacedtelevision raster scan of 525 horizontal scanlines; i.e., 262 /2 oddlines and 262 /2 even lines. The illustrated upper casecharacters are 28scanlines high, the individual scanlines being labeled as h through hEach scanline has a duration of about 64 microseconds. A basic systemclock produces a plurality of pulses during each scanline andeffectively divides each scanline into a plurality of elemental spaces,shown as the horizontal divisions or elements in FIG. 3. Each elementcorresponds to a time duration of about nanoseconds, and the firstcharacter W was arbitrarily chosen as starting at a time t or 100elements (i.e. l0 microseconds) after the beginning of the horizontalscanline reference.

The row of characters shown in FIG. 3 occupies the portion of the screenr to about t so it takes the scanning beam about 9 microseconds totraverse the portion shown during each scanline. During the firstscanline, labeled h,, the top stroke of the character W" is displayed byturning the scanning beam "on" for the period two I104, I113 tug, and 2[13 After a space? of 4 elements, the beam is again turned on for theperiod I r to produce the top stroke of the 1" and then from 2, r forthe top stroke of the E, etc. The next horizontal scanline of aninterlaced raster scan is h;,, which happens to require the same strokesas h for the character shown. For the scanline h,, the beam is turned onfor the period r r r and 2 [129 for the W; 35 -t 39 for the 1; rm. 11for the E;" and so on. In this manner, and with the help of theretentivity of vision of the eye, the separate character strokesproduced during each scanline give the impression of complete characterson the display screen.

It is seen that the characters have differing widths and that eachcharacter does not occupy an equal size character space on the displayscreen. For example,

among the characters shown, the number of elemental widths occupied byeach character are as follows: t- ,1i%t;,il: an shisf a u e calledproportional spacing" is a feature of the abovereferenced copendingapplication, and is described herein only as an illustration of aparticular type of character generator with which the techniques of thepresent invention can be utilized. It will become clear, however, thatthe principles of the present invention apply equally well to charactergenerator systems wherein each character occupies the same width on thedisplay screen.

Returning to the description of FIG. 2, the storage means 100 includes asix-level shift register having a plurality of stages, the number ofstages being determined by the maximum number of characters to bedisplayed in a row on the display device. The received signals arestored in sequence in the shift register. Upon the appropriate commands,the six bits representative of the character in the last stage of theshift register are read out and then restored to the first stage of theregister to be recirculated. The character read out is referred to asthe specified character and its representative bits or signals as thespecified character signals.

The timing generator means 200 receives synchronizing signals from thedisplay device; namely the vertical and horizontal sync signals. Thetiming generator means 200 includes a megacycle keyed oscillator whichproduces basic clock pulses every 100 nanosecends. The oscillator iskeyed by the horizontal sync signals from the display device. The timinggenerator also includes various counters which keep track of the numberof lines scanned by the display up to a given time. When the displayscan is in a row area (only a single row of displayed characters isconsidered for ease of explanation) the counters produce signals thatindicate which line of the row is being scanned.

The stroke generator 300 receives the specified character signals andline information from the timing generator means and, in responsethereto, generates stroke bits suitable for controlling the display toproduce the appropriate stroke of the specified character. The strokegenerator means typically includes a readonly memory which is addressedby the received character information and by line information. Forexample, if the received information indicates that the specifiedcharacter is a W" and that the present display scanning line is h5 (FIG.3), then the memory output stroke bits will be sequential signalsinstructing the scanning beam to turn on for the intervals t r n: 120and '12s 130- The specified character signals are also received by thespacer detector 300 which determines the width of the specifiedcharacter and generates a spacer timing signal which depends upon thetime when the horizontally scanning beam passes out of the display areaneeded to produce the specified character. The spacer timing signals areused to shift the recirculating storage means so that the next characterin sequence becomes the new specified" character in the last stage ofthe shift register. The appropriate stroke of the new specifiedcharacter is then generated. The spacer detector also generates acoordinating timing signal, synchronized with a spacer timing signal,for controlling the timing associated with the generation and readout ofstroke bits.

The operation of the apparatus of FIG. 2 can be better understood byvisualizing the letters of FIG. 3 as being the beginning of the sequenceof, say, twenty characters to be displayed in a single row. The sequenceof binary coded character-representative signals are read into therecirculating storage and are stored with the W, the I, the E, etc. inadjacent stages of the shift register. The sync signals from the displayare fed to the timing generator 200, and counters in the timinggenerator count the number of horizontal scanlines of a display fieldscansion until, after a predetermined number of lines, the display rowarea is reached. The scanlines within the display row are thenseparately counted by the timing generator 200, the first scanline beingh, (FIG. 3).

The scanline h, begins its left to right scan at time reference, t whichrepresents the time at which the horizontal sync signal keys the 10megacycle basic clock oscillator. A predetermined time after t thesignals representative of the character in the last stage of the shiftregister (i.e., the specified character W) are fed to the strokegenerator 300 and to the spacer detector 400. The stroke generatorgenerates stroke bits which instruct the scanning beam to turn on" forthe appropriate time intervals (t 2 r r and r r for character W," line11,). The spacer detector 400 decodes the character-representativesignals and determines the width of the specified character. In the caseof he the ch a te s.3 r,,s ta d is o wide, or, in other words, itrequires a 31 clock pulse duration for display. The spacer detectoraccordingly generates a spacer timing signal at a time reference r thatis, 31 clock pulses after the initiation (at t of display of thespecified character.

The spacer timing signal is fed to the recirculating storage 100 andused to shift the positions of the character-representative signals inthe shift register. The W" is shifted back to the first stage of theshift register and the I moves into the last stage to become the newspecified character. Similarly, each character moves up one position sothat the E is in the next to last stage, the L is in the second fromlast stage, and so on. A coordinating timing signal, which occursshortly after the spacer timing signal, is also generated by the spacerdetector. The coordinating timing signal is fed to the stroke generator.

During the time after occurrence of the spacer timing signal, thescanning beam moves along the space" area beginning with the elementaldivision r (FIG. 3). Also during this time, the binary signalsrepresentative of the character I are fed from the last stage of theshift register to the stroke generator 300 and to the spacer detector400. The stroke generator 300 generates stroke bits which instruct thescanning beam to turn on for a period of four elemental divisions. Thecoordinating timing signal (from the spacer detector 400) controls thestart of the readout of stroke bits to occur at h so that the scanningbeam turns on for the time interval r r Meanwhile, the spacer detectordecodes the new character-representative signals and determines that thespecified character (I) is four elemental divisions wide. The spacerdetector accordingly generates the next spacer timing signal at the timereference r that is, four clock pulses after the initiation (at r of thedisplay of the specified character I."

In a similar manner the remaining top slices of each of the twentycharacters are produced during the scanline h For the complete scanline,the spacer timing signals circulate the character-representative signalsin the shift register by exactly one full cycle, so that at the end ofscanline h, the W is again in the last stage of the shift register, theI is in the next to last stage, etc. The next horizontal scanline of theinterlaced raster scan is h The horizontal sync signal associated withthe beginning of the scanline h is counted by the timing generator 200and the resultant new line information is fed to the stroke generator.The appropriate strokes of each of the twenty characters are thengenerated as previously described, and in this manner the characterstrokes for each odd-numbered scanline are successively formed. At theend of the vertical field scansion the scanning beam is retracedwhereupon it scans the even-numbered scanlines and forms the remainingcharacter strokes.

FIG. 4 illustrates the functioning of the stroke generator 400 of FIG.2. The stroke generator includes a read-only memory (ROM) unit 41 .1which receives the specified character signals as well as lineinformation from the timing generator 200 (FIG. 2). Read-only memoriesthat are addressable with multiple inputs are well known in the art andare described, for example, inan article by F. Kvamme which appeared atpage 88 of the Jan. 5, 1970 issue of Electronics. The ROM 411 generatesthirty-one stroke bits which are entered in parallel into theparallel-in-serial-out shift register 412. The stroke bits are clockedout serially using the basic clock pulses from the keyed oscillator intiming generator 200. The readout of stroke bits is initiated by theenabling of the register 412, which is accomplished by coordinatingtiming signals from the spacer detector 300. Most of the charactersconsist of less than thirty-one stroke bits. For example, the top strokeline of an 1 consists of only four stroke bits, e.g. 11 ll. Theremaining bits (five to thirty-one) to be read out of the ROM are Os.These Os do not have a chance to be read out, however. After the fourthstroke bit (still using the I as an example), a timing signal fromspacer detector 300 shifts the recirculating storage means and a newspecified character is read into the ROM 411, at the same time disablingreadout of stroke bits from the register 412. The shift register 412 isreloaded and does not begin its next readout until enabled again by thecoordinating timing signal. The spacer detector 300 also producesbetween-character spacer timing pulses on a line 301, these pulses beingutilized in the present invention in a manner to be describedhereinafter.

The stroke bits, read out over line 413 can be combined with standardpicture video (using conventional keying techniques) to produce acomposite television picture having unedged title information.Alternatively, a commerical edging equipment, as described in thebackground portion of this specification, can be used to produce titleinformation having a conventional type of edging.

As above-stated, the foregoing description was intended to illustrate aparticular type of character generator with which the techniques of thepresent invention can be utilized. Referring to FIG. there is shown ablock diagram of circuitry in accordance with the present invention. Astroke generator means 500 is similar in function to the strokegenerator 400 of FIG. 4, and

has included therein a ROM 5'11 and a parallel-inserial-out shiftregister 512 that functions in the same manner as the register 412 ofFIG. 4. Once again, the ROM receives specified character signals andline information from other portions of a character generator system andgenerates a plurality of stroke bits that are entered in parallel intothe register 512. As before, the register 512 is enabled by coordinatingtiming signals and its readout, (over a line 513), is synchronized withbasic clock signals.

The stroke generator 500 includes a buffer register 514 which, in thisembodiment, consists of only two levels. In addition to the thirty-onestroke bits which the ROM generates and enters into the register 512,the ROM Slll generates two additional bits, called code bits, for eachstroke. These bits are entered into buffer 514 which serves the purposeof holding" a pair of outputs, denoted S and S at a specified inputlevel (determined by the two entered bits) for the duration of theindividual stroke. Thus, for example, if a particular stroke were tohave its two code bits at the I level, the buffer 514 would hold theoutputs on the lines S and S high until the stroke bits for theparticular stroke had been completely read out of register 512 over line513.

A decoding means 600, shown in dashed line, receives the stroke bits andthe code bits and generates video control signals, designated E and E,,,that are suitable for controlling conventional keying circuitry and ascanned display to present contrasted images of characters to bedisplayed. The decoding means 600 includes a level generator 601 thatreceives digital stroke bits on line 513 and produces a continuousstroke signal on an output line 602. The level generator 601, typicallya flip-flop, is utilized in conventional fashion to convert digitalstroke bits to a continuous rectangular-wave signal E of the typesketched in FIG. 5.

The stroke signal E is received by a horizontal delay circuit 603 thatis shown in detail in FIG. 6. The circuit 603 includes a pair of D-typeflip-flops, designated as flip-flops 604 and 605. D-type flip-flops arewell-known in the art as having at least two inputs sometimes designatedD and T. The unit is designed such that its output follows the input atD after the occurrence of a clock pulse at the T input. In the circuit603, these devices are utilized to generate processed stroke signalsthat are delayed by one and two clock pulses from the original strokesignal E.

The stroke signal E is received at the D input of fiipflop 604 whichreceives basic clock signals at its T input. Since the stroke signal wasoriginally generated in synchronism with the basic clock, thepositive-going edge of the stroke signal E will occur at substantiallythe same time as a basic clock signal at T. In order for the input at Dto appear at the flip-flop output, the clock pulse at T must occur afterthe signal at D. Therefore, the output of flip-flop 604, designated asE,,,,,,,,, will start one clock pulse after the beginning of strokesignal E; in other words, E is delayed by one clock pulse from E.

The output of flip-flop 604 (E,,,,,,,,) is received at the D input offlip-flop 605 which also receives the basic clock at its input T. Thisunit acts similarly to the flipfiop 604 in that it produces an output,designated E that is delayed from E by one clock pulse. The originalstroke input E is made available as an output of the circuit 603 anddesignated as E so that three processed stroke signals designatedE,,,,,, E,,,,,,,,, and E are available as outputs. These stroke signalshave respective delays from the original stroke signal of zero clockpulses, one clock pulse and two clock pulses.

Referring again to FIG. 5, the processed stroke signals from circuit 603are each fed as inputs to an OR gate 610 that is designated herein as akeying gate.+ The signal E is also coupled as an input to an AND gate611 designated herein as a video gate. The gate 611 has two additionalinputs that will be described hereinafter, but for the present it willbe assumed that these inputs are at a logical I level so that the outputof video gate 611 tracks the input E,,,,,,,,. The output of keying gate610, designated E,, is typically coupled to an insert keyer thateffectively opens slots in the picture video. These slots," being anabsence of video, will appear black on a display if no light video isinserted therein. The signal E controls the insertion of title strokesat a predetermined brightness level, generally white level.

The manner in which the circuitry described to this point is utilized toproduce strokes having contrasted edges can be described with the aid ofFIG. 7. The displayed characters at the top of the FIGURE are similar inform to the characters depicted in FIG. 3. In FIG. 7, however, each fullcharacter, including edging, is formed from 30 scanlines or strokes,with the main unedged portion of the character requiring the same 28scanlines as the characters of FIG. 3. The portions of FIG. 7 below thecharacters indicate the timing relationships of certain signalsassociated with the formation of various parts of the illustratedcharacters. These signals are shown in synchronism with the illustratedcharacters.

The scanlines during which the characters illustrated in FIG. 7 areformed are sequentially designated from 1 to 30, the designation ofselected scanlines being labeled to the left of the characters. Thefirst set of timing diagrams are associated with scanline 2 and areuseful in explaining the operation of the portions of FIG. 5 describedup to this point. The first line of the group shows the timing of thestroke signal E that is used to form scanline 2 of the sequence ofcharacters shown in FIG. 7. This signal also becomes E as was describedin conjunction with FIG. 6. The next two lines of the timing diagramrespectively show signals E and E,,,,,,,; i.e., two sets of signals thatare delayed one and two clock pulses from E,,.,,. The fourth line of thediagram shows the timing of the signal designated E in FIG. 5. By actionof the OR gate 610, the signal E, is seen to be present when E e or Emor Er is present The fifth and final line of this group shows E, which,for this particular example, corresponds to E,,,,,,,,. The two signals5,. and E,,, when viewed together, illustrate the formation of thestrokes of the three characters T, H, and 1". The edges on eachcharacter (for this scanline) are formed by an overlap" of the keyingfor each stroke of the characters, the overlap on each side of eachstroke being one clock pulse in length.

Referring again to FIG. 5, the signal E in addition to being received bythe gates 610 and 611, is coupled to a stroke portion sensor unit 620.The unit 620, which also receives spacer timing pulses over line 301(see FIG. 4), effectively determines the occurrence of the differentparts or portions of the video events that make up the stroke for aparticular character. In the present embodiment, the video events areclassified as odd or even events. For example, in FIG. 7, scanline 2 ofthe character H is made up of two distinct stroke portions that formslices of the sides of the H. For E,,,,,,,,, these stroke portions areseen to occur (in the timing diagram scale) from t=273l for the firststroke portion and from r=42-46 for the second stroke portion. The firststroke portion is considered an odd stroke portion (as would be thethird, fifth, etc. stroke portions if they occurred), while the secondstroke portion is considered an even stroke portion (as would be thefourth, sixth, etc. if they occurred).

The circuitry of the stroke portion sensor 620 produces an output of anodd output line 621 during occurrence ofa characters odd stroke portionsand an output on an even output line 622 during occurrence of acharacters even stroke portions. The unit 620 is shown in further detailin FIG. 8 wherein there is depicted a toggle-type flip-flop 625 and aD-type flipflop 626.

Each of the flip-flops receives, as a reset input, the spacer timingpulse over line 301. Accordingly, the two flip-flops are reset so as tohave a logical 0 output between successive characters of charactersequence. The toggle flip-flop 625 receives E as an input and istriggered to alternate output levels by the leading edges of successivestroke portions. Thus, the output of flip-flop 625, designated E isinitially at a logical 0 (having been reset) and is switched to alogical 1 output level by the leading edge of the first stroke portionof the stroke associated with a new character. The subsequent strokeportions of the character cause E to alternate between 0 and 1 such thatE is a logical 1 during the odd" stroke portions of the particularcharacter.

The output of flip-flop 625, in addition to being utilized as the Eoutput on line 621, is fed to the D input of the flip-flop 626. Thisflip-flop, which receives E,,,,,,,, at its T input, is reset to alogical 0 output between characters, but stays at a 0 output after thefirst stroke of a new character. When the leading edge of the firststroke portion is received at the T input of gate 626, the D input ofthe gate is still at a logical 0 level due to the small inherentpropagation time of the toggle flip-flop 625. As a result, the 1 inputat D is received after the 1 input at T, and the output of gate 626,designated E remains at 0. When, however, the leading edge of the secondstroke portion is received at the T input of gate 626, the D input isstill at 1 (again due to the propagation of gate 625), so that theoutput of gate 626 goes to 1 during the second stroke portion of thecharacter. In this manner, the output E on line 622 is at a logical Ilevel during a characters even stroke portions and at a 0 level duringthe character's odd stroke portions.

Returning to FIG. 5, the outputs of the stroke portion sensor 620 arecoupled to a pair of NAND gates 640 and 650. The gate 640 receives asone input the E signal on line 621 and, as its other input, one of thecode bits S The gate 650 receives as inputs the signal E on line 622 andthe code bit S The outputs of the gates 640 and 650 are received byvideo gate 611 which, it will be recalled, receives as its third inputsignal E,,,,,,,,. In operation, the outputs of the gates 640 and 650selectively disable the video gate 611 during prescribed strokeportions, the code bits being determinative of which portions of thestroke are disabled. When one or both of the code bits are 0, the NANDgate which receives the code bit necessarily has a 1 output.Consequently, the output of that particular gate or gates does notdisable the video gate 611 during any portion of the stroke of theparticular character to which the code bits correspond. For example, inthe case of scanline 2 as shown in FIG. 7, the code bits S and S areboth 0 for all three of the characters shown. This means that theoutputs of the gates 640 and 650 are at 1 during formation of thesecharacters, and the generation of the signals E,, and E, is determinedsolely by action of the circuitry described above in conjunction withthe set of timing diagrams for scanline 2.

The overall operation of the circuitry of FIG. 5 is best illustratedwith the aid of the timing diagrams of FIG. 7. The next group of timinggraphs to be considered is the one associated with scanline 13 of thecharacters shown in FIG. 7. This scanline forms parts of the verticalleg of both the T and the and forms a part of the legs of the H as wellas the edge above the central bar of this letter. The code bitsassociated with each of the characters are indicated in the FIGURE belowthe timing graphs. The code bits for both the T and the 1" are seen tobe 0s, while the code bits for the H are S,,,, =0 and S ,,,.,,=l.

Considering the T first, the stroke signal for scanline 13 is four clockpulses wide and timed such that E occurs from t=0 to t=l4. The formationof the outputs of the horizontal delay circuit 603 (E E,,,,,,,,,' andE,,,,,,,) as well as the formation of E,, are similar in principle tothe description of these operations with respect to scanline 2. In thiscase, E extends from t=9-l5 and, as above, overlaps the signal E by oneclock pulse on each side. The signal E begins coincidentally withE,,,,,,,, since the stroke portion of the T being considered here (theonly portion for this scanline) is an odd portion. The signal E remainson until the spacer timing pulse on line 301 resets the stroke portionsensor 620 (FIG. 8). The spacer timing pulses on line 301, as describedabove, occur in the space period between characters. In the presentembodiment, these pulses occur one clock pulse after the last bit of Efor each character. In FIG. 7, this means that the spacer timing pulsesoccur at F24, F47 and t=66. Thus, the signal E for the T continues untilt=24 whereupon the stroke portion sensor is reset by the spacer timingpulse and E goes off. In the case of the T, there is no signal E sinceonly one stroke portion is present. Also, the existence of E does notresult in any disabling of the video gate 611 since the code bit S 0 forscanline 13 of the T. The signal E, is therefore seen to correspond tothe signal E with E, occurring from Fl0l4. It should be noted that theproduction of this particular stroke of T would have been the same if Shad been 1 since, in any event, the absence of a signal E would haveprevented a disable signal being generated by the gate 650. In instancessuch as these, however, code bits which effect only nonexistent strokeportions are considered as being 0 for consistency, although their valuein these circumstances makes no practical difference.

Considering, now, the H, the stroke signal for scanline 13 consists ofthree portions which are timed such the E occurs from F27-31, 1=32-4land t=42-46. These stroke portions result in an E, that extends fromt=26-47. The signal E reflects only the first and third of the threeportions, and is active from t=27-32 and r=42-47. The signal E reflectsthe second portion and is active from i=32-42. As indicated to the rightof the timing graphs, the code bits for scanline 13 of the H are S O andS ,.,.,,=l. This means that only gate 650 (FIG. 5) can disable videogate 611 and this disabling, which occurs during E,.,..,,, is effectedfrom l==3242. The resultant E, consists of the first and third portionsof E,,,.,,,,; viz., r=27-31 and r=42-46. The second portion of E doesnot become part of E, since gate 611 is disabled by E during thisportion. Thus, the long keying signal E. and the two short portions ofE, are utilized to form the desired scanline 13 of the H.

Scanline 13 of the is routine with both code bits being zero for thischaracter.

The next group of timing graphs relates to scanline 26, and thisscanline of the is of interest in that it forms the edging above thelower arm of the character. The slices of the other two characters areformed in routine manner. The code bits for the 1 are S l and S ,,=0. Asa result, E, is disabled during the first of the two illustrated strokeportions. The signal 15,, extends the length of the character (in thetime domain), and a superimposed E, signal from Fol-65 forms the desiredslice of the character.

The next group of timing graphs relates to scanline 8, and this scanlineof the T is of particular interest in that it forms part of the shadingbelow the crown of the T. This type of selective shading is notavailable with conventional edging equipments. The stroke signal is madeup of five portions. The code bits for the T for this scanline areS,,,,,,=0 and S =l so E, is disabled during the second and fourth strokeportions to achieve the desired character slice. Again, the tworemaining character slices are formed in the routine fashion with codebits all 0.

The last group of timing graphs of FIG. 7 relates to scanline 30 whichforms the bottom edging below all three characters. This is achieved bydisabling E, during all stroke portions of all characters so that onlykeying signal E;, is generated. Accordingly, all code bits ofsignificance are 1.

Referring to FIG. 0, there is shown another embodiment of the inventionin which the ROM 511 generates three code bits, the third code bit beingdesignated as S,,. In this embodiment, the decoding means 600 includestwo additional gates, an OR gate 660 and an AND gate 670. In otherrespects, the circuit of FIG. 9 is the same as the circuit of FIG. 5.The OR gate 660 receives as inputs the signals E and E from the strokeportion sensor 620. The output of OR gate 660 and the code bit 5,, arereceived by AND gate 670, the output of which is fed as an additionalinput to the keying gate 610.

The bit S is utilized to control a situation wherein an edging orshading area is to appear continuously between successive strokeportions of a character. The use of this additional bit as part of thecharacter strokes allows achievement of certain effects that wereobtained in the previous embodiment, but with different sets ofsequential stroke bits than were used with that embodiment. An exampleof the operation of the system of FIG. 9 is illustrated with the aid ofFIG. 10 which deals with formation of scanline 13 of an 11 using thissystem. It will be recalled from FIG. 7 that scanline 13 of the H isformed from a keying signal that extends from t==26-47 and video strokeportions that extend from F2741 and t=4246. With the equipment of FIG.5, the desired keying and video signals had been achieved by forming astroke that consisted of three portions (see FIG. 7). The middle strokeportion was utilized to form the edging or shading above the central barof the H. By fixing the code bit S at 1, video was inhibited during thiscentral stroke portion to achieve the desired effect.

With the system of FIG. 9, the desired pattern can be formed utilizingstroke bits that yield a stroke signal which has only two separatedportions that represent the video needed for the legs of the H. Theedging above the horizontal bar of the H is achieved by having thestroke generator produce the third code bit S as a 1 so that an edge isautomatically produced between the two stroke portions.

In FIG. 10, the stroke signal for scanline 13 is seen to consist of twoportions which are timed such that E occurs from t=27-3l and t=42-46.The signal E which starts contemporaneously with E remains on until t=46whereupon the signal E goes on. It is therefore seen from FIG. 9, thatthe output of OR gate 660 is active from t=27 to the end of thecharacter. With 8, equalling l, the output of gate 660 will cause theAND gate 670 to have a 1 output during this same interval, with theresult that the keying gate 610 is turned on during this time. Thesignal E thus extends the length of the character (in the time domain)and yields the desired edge between the video stroke portions.

FIGS. 9 and show the manner in which additional code bits can beutilized to achieve special effects. It will be understood that theillustrated embodiments could be modified in various ways within thespirit and scope of the invention. For example, the stroke generatorcould be preset to produce larger numbers of code bits to obtaindifferent combinations of keying and video events or to obtain variouskeying signals for utilization in obtaining different colored displayeffects.

We claim:

1. in an apparatus that receives characterrepresentative signals andgenerates video control signals and keying control signals that aresuitable for controlling a scanned display to present self-contrastingcharacter images superimposed on a background, the combinationcomprising:

stroke generator means responsive to said characterrepresentativesignals for generating a stroke for each scanline of a character to bedisplayed, said stroke comprising a plurality oftime sequential bitscorresponding to a sequence of character display events and a pluralityof code bits generated simultaneously with said time sequential bits fordistinguishing between contrasting portions of the sequence of characterdisplay events; and

decoding means responsive to said time sequential bits and said codebits for generating keying control signals and video control signalssuitable for controlling the scanned display to present theselfcontrasting images of the characters to be displayed.

2. The combination as defined by claim 1 wherein said code bits arerepresentative of the keying and video portions of the sequence ofcharacter display events.

3. The combination as defined by claim 2 wherein said decoding meansincludes horizontal delay means for receiving signals representative ofsaid time sequential bits and generating delayed versions of saidsignals.

4. The combination as defined by claim 1 wherein said decoding meansincludes stroke portion sensing means for sensing various portions ofsignals represented by said time sequential bits and for generatingdifferent output signals during said various portions.

5. The combination as defined by claim 4 wherein said decoding meansincludes means responsive to the outputs of said stroke portion sensingmeans and to said code bits for producing signals that disable thegeneration of a video signal during selected stroke portions.

6. The combination as defined by claim 5 wherein said code bits aredeterminative of which portions of the character display events are tobe disabled.

7. The combination as defined by claim 6 wherein said stroke portionsensing means senses even and odd portions of the signals representativeof said time sequential bits.

8. In an apparatus that receives characterrepresentative signals anddisplay synchronizing signals and generates video control signals andkeying control signals that are suitable for controlling a scanneddisplay to present self-contrasting character images superimposed on abackground, the combination comprising:

stroke generator means responsive to said characterrepresentativesignals and said synchronizing signals for generating a stroke for eachscanline of a character to be displayed, said stroke comprising aplurality of time sequential bits corresponding to a sequence ofcharacter display events and first and second code bits generatedsimultaneously with said time sequential bits for distinguishing betweencontrasting portions of the sequence of character display events; and

decoding means responsive to said time sequential bits and said codebits for generating keying control signals and video control signalssuitable for controlling the scanned display to present theselfcontrasting images of the characters to be displayed.

9. The combination as defined by claim 8 wherein said decoding meansincludes stroke portion sensing means for sensing the odd and evenportions of signals represented by the time sequential bits and forgenerating first and second output signals during said off and evenportions respectively.

10. The combination as defined by claim 9 wherein said first code bitindicates that video is to be inhibited during the odd portions of thesignals represented by the time sequential bits, and the second code bitindicates that video is to be inhibited during the even portions of thesignals represented by the time sequential bits. I

11. The combination as defined by claim 10 wherein said decoding meansfurther includes a first gate which receives as inputs said first codebit and said first output signal and produces a first inhibit signalwhen its inputs are present simultaneously, and a second gate whichreceives as inputs said second code bit and said second output signaland produces a second inhibit signal when its inputs are presentsimultaneously, said first and second input signals being adapted toinhibit video.

12. The combination as defined by claim 11 wherein said decoding meansincludes horizontal delay means for receiving signals representative ofsaid time sequential bits and generating delayed versions of saidsignals.

13. The combination as defined by claim 12 wherein said decoding meansincludes a keying gate and a video gate, said keying gate receiving thesignals representative of the time sequential bits and all delayedversions thereof, and said video gate receiving one of the delayedversions of the signals representative of the time sequential bits.

14. The combination as defined by claim 13 wherein said video gatereceives as inputs said first and second input signals.

15. The combination as defined by claim 14 wherein said keying gate isan OR gate and said video gate is an AND gate.

16. The combination as defined by claim 14 wherein said stroke generatormeans generates a third code bit for each character to be displayed andwherein said decoding means further includes a third gate which receivessaid first and second output signals and a fourth gate which receivessaid third code bit and the output of said third gate, the output ofsaid fourth gate being received as an input by said keying gate.

17. The combination as defined by claim 16 wherein said third gate is anOR gate and said fourth gate is an AND gate.

18. The combination as defined by claim 17 wherein said keying gate isan OR gate and said video gate is an AND gate.

19. A method of receiving character-representative signals andgenerating video control signals and keying control signals that aresuitable for controlling a scanned display to present self-contrastingcharacter images, comprising the steps of:

a. generating a stroke for each scanline of a character to be displayed,said stroke comprising a plurality of time sequential bits correspondingto a sequence of character display events and a simultaneously generatedplurality of code bits that distinguish between contrasting portions ofthe sequence of character display events;

b. generating said keying control signals from said time sequentialbits; and

c. generating said video control signals from selected portions of saidtime sequential bits, said code bits being determinative of whichportions of said time sequential bits are selected.

1. In an apparatus that receives character-representative signals andgenerates video control signals and keying control signals that aresuitable for controlling a scanned display to present self-contrastingcharacter images superimposed on a background, the combinationcomprising: stroke generator means responsive to saidcharacterrepresentative signals for generating a stroke for eachscanline of a character to be displayed, said stroke comprising aplurality of time sequential bits corresponding to a sequence ofcharacter display events and a plurality of code bits generatedsimultaneously with said time sequential bits for distinguishing betweencontrasting portions of the sequence of character display events; anddecoding means responsive to said time sequential bits and said codebits for generating keying control signals and video control signalssuitable for controlling the scanned display to present theself-contrasting images of the characters to be displayed.
 2. Thecombination as defined by claim 1 wherein said code bits arerepresentative of the keying and video portions of the sequence ofcharacter display events.
 3. The combination as defined by claim 2wherein said decoding means includes horizontal delay means forreceiving signals representative of said time sequential bits andgenerating delayed versions of said signals.
 4. The combination asdefined by claim 1 wherein said decoding means includes stroke portionsensing means for sensing various portions of signals represented bysaid time sequential bits and for generating different output signalsduring said various portions.
 5. The combination as defined by claim 4wherein said decoding means includes means responsive to the outputs ofsaid stroke portion sensing means and to said code bits for producingsignals that disable the generation of a video signal during selectedstroke portions.
 6. The combination as defined by claim 5 wherein saidcode bits are determinative of which portions of the character displayevents are to be disabled.
 7. The combination as defined by claim 6wherein said stroke portion sensing means senses even and odd portionsof the signals representative of said time sequential bits.
 8. In anapparatus that receives character-representative signals and displaysynchronizing signals and generates video control signals and keyingcontrol signals that are suitable for controlling a scanned display topresent self-contrasting character images superimposed on a background,the combination comprising: stroke generator means responsive to saidcharacter-representative signals and said synchronizing signals forgenerating a stroke for each scanline of a character to be displayed,said stroke comprising a plurality of time sequeNtial bits correspondingto a sequence of character display events and first and second code bitsgenerated simultaneously with said time sequential bits fordistinguishing between contrasting portions of the sequence of characterdisplay events; and decoding means responsive to said time sequentialbits and said code bits for generating keying control signals and videocontrol signals suitable for controlling the scanned display to presentthe self-contrasting images of the characters to be displayed.
 9. Thecombination as defined by claim 8 wherein said decoding means includesstroke portion sensing means for sensing the odd and even portions ofsignals represented by the time sequential bits and for generating firstand second output signals during said off and even portionsrespectively.
 10. The combination as defined by claim 9 wherein saidfirst code bit indicates that video is to be inhibited during the oddportions of the signals represented by the time sequential bits, and thesecond code bit indicates that video is to be inhibited during the evenportions of the signals represented by the time sequential bits.
 11. Thecombination as defined by claim 10 wherein said decoding means furtherincludes a first gate which receives as inputs said first code bit andsaid first output signal and produces a first inhibit signal when itsinputs are present simultaneously, and a second gate which receives asinputs said second code bit and said second output signal and produces asecond inhibit signal when its inputs are present simultaneously, saidfirst and second input signals being adapted to inhibit video.
 12. Thecombination as defined by claim 11 wherein said decoding means includeshorizontal delay means for receiving signals representative of said timesequential bits and generating delayed versions of said signals.
 13. Thecombination as defined by claim 12 wherein said decoding means includesa keying gate and a video gate, said keying gate receiving the signalsrepresentative of the time sequential bits and all delayed versionsthereof, and said video gate receiving one of the delayed versions ofthe signals representative of the time sequential bits.
 14. Thecombination as defined by claim 13 wherein said video gate receives asinputs said first and second input signals.
 15. The combination asdefined by claim 14 wherein said keying gate is an OR gate and saidvideo gate is an AND gate.
 16. The combination as defined by claim 14wherein said stroke generator means generates a third code bit for eachcharacter to be displayed and wherein said decoding means furtherincludes a third gate which receives said first and second outputsignals and a fourth gate which receives said third code bit and theoutput of said third gate, the output of said fourth gate being receivedas an input by said keying gate.
 17. The combination as defined by claim16 wherein said third gate is an OR gate and said fourth gate is an ANDgate.
 18. The combination as defined by claim 17 wherein said keyinggate is an OR gate and said video gate is an AND gate.
 19. A method ofreceiving character-representative signals and generating video controlsignals and keying control signals that are suitable for controlling ascanned display to present self-contrasting character images, comprisingthe steps of: a. generating a stroke for each scanline of a character tobe displayed, said stroke comprising a plurality of time sequential bitscorresponding to a sequence of character display events and asimultaneously generated plurality of code bits that distinguish betweencontrasting portions of the sequence of character display events; b.generating said keying control signals from said time sequential bits;and c. generating said video control signals from selected portions ofsaid time sequential bits, said code bits being determinative of whichportions of said time sequential bits are selected.